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Phinitylabs

Physical Design Lead

  • Seen live on Phinitylabs' site today
  • Senior
Pay
Not stated
Location
San Francisco
Open for
12+ days
First seen
Oct 23, 2026

Posting record

No flags

Open 12+ days

The posting's record, oldest first
  1. Phinitylabs' site dates the posting
  2. Ghostless first sees this listing
  3. Last checked: still up
How we know

It hasn't been reposted, listed twice, or left up unusually long, and the posting doesn't say it's a talent pool.

Ghostless records the day it first sees a posting, so a repost can't reset its age. This one was already up when Ghostless started tracking Phinitylabs, so its true age is longer.

Last checked Nov 4, 2026.

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What it asks of you

10+ years of experience
“ecutives from top chip companies, post-training chip-design models at NVIDIA, AI for formal verification research, previous exits, and over 10 years of experience building chips at NVIDIA, Intel, Mediatek, and others.” (quoted from the posting)

What the posting discloses

Not stated: Pay, real vacancy, AI screening.

Why these three

Ontario requires postings from employers with 25 or more staff to state the pay, whether the vacancy exists, and whether AI screens applicants.

Some employers add pay only on their own site. Check the original posting before you rule it out.

Skills mentioned

About the role

Phinity is an AI research lab focused on solving chip design. The bottleneck to AGI is compute, and we enable AI agents to tape-out chips autonomously, from architecture to post-silicon. We are building RL environments, agent infrastructure, and evaluation systems to accomplish this. Our team brings together deep AI and silicon expertise, including leaders and executives from top chip companies, post-training chip-design models at NVIDIA, AI for formal verification research, previous exits, and over 10 years of experience building chips at NVIDIA, Intel, Mediatek, and others.

We are hiring a Physical Design Lead .

You will be responsible for

  • Leading PD flows and optimization of block-level to full-chip level optimizations
  • Define Synthesis to layout flows, including PDN, clock-trees, PVT corners and custom cell definitions. Responsible for implementing characterization flows for custom cells and memory blocks.
  • Responsible for executing IP and Fullchip design optimizations working with PD engineers. Identify areas of optimization in design utilization, power grid and clock network within the design.
  • Responsible for delivering tapeout ready design optimized for the target PPA, and utilizing the in-house capability on prompt-to-GDS.

Why Phinity

  • Work directly with the founders to shape the strategy and growth of an ambitious AI research lab
  • Take ownership of high-impact initiatives across business strategy, partnerships, and company operations
  • Collaborate with leading AI researchers and hardware experts at the frontier of autonomous chip design

Benefits include

  • Health insurance
  • Retirement plans
  • Unlimited PTO
  • Paid parental leave
  • Lunch and dinner provided in-office

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