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Architect Labs

Vice President of ASIC Engineering

  • Seen live on Architect Labs' site today
  • Mid level
Pay
Not stated
Location
Palo Alto
Open for
4 days
First seen
Oct 31, 2026
Apply on Architect Labs' site (opens in a new tab)

Posting record

No flags

Open 4 days

The posting's record, oldest first
  1. Architect Labs' site dates the posting
  2. Ghostless first sees this listing
  3. Last checked: still up
How we know

It hasn't been reposted, listed twice, or left up unusually long, and the posting doesn't say it's a talent pool.

Ghostless records the day it first sees a posting, so a repost can't reset its age.

Last checked Nov 4, 2026.

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What the posting discloses

Not stated: Pay, real vacancy, AI screening.

Why these three

Ontario requires postings from employers with 25 or more staff to state the pay, whether the vacancy exists, and whether AI screens applicants.

Some employers add pay only on their own site. Check the original posting before you rule it out.

Skills mentioned

About the role

About Architect Labs

Architect is a frontier AI lab for custom silicon. We partner with frontier labs, clouds / neoclouds, physical AI companies, and advanced fabs to tape-out custom chips co-designed for next-generation AI workloads. Our goal is to compress end-to-end software to silicon timelines, and maximize intelligence per watt and per dollar for the world. We are a small exceptional team across silicon, systems, software and frontier AI. Our team have led research teams at nearly every frontier AI lab, and at some of the most complex SoCs in the world.

What You'll Do

Own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. Build a fundamentally faster, AI-native chip-development flow, using automation, intelligent agents, and data-driven feedback loops to accelerate design iteration, verification, closure, and engineering productivity. Lead a world-class team, set an uncompromising bar for PPA and silicon quality, and personally drive the most consequential technical and execution decisions.

What We'd Like to See

  • Repeated tapeout success: Direct leadership of multiple complex, production-volume ASIC or SoC programs, ideally at advanced process nodes.
  • End-to-end ASIC mastery: Deep expertise spanning RTL, functional verification, synthesis, timing closure, physical implementation, DFT, signoff, and silicon bring-up.
  • Methodology innovator: A track record of transforming design flows through automation, ML/AI-assisted EDA, verification productivity, or scalable engineering infrastructure—not merely operating established processes.
  • Execution excellence: A demonstrated ability to deliver demanding programs with strong first-silicon outcomes and disciplined engineering tradeoffs.
  • Elite team builder: A record of recruiting, developing, and leading world-class silicon engineers and technical leaders.
  • Hands-on leadership: Credibility to resolve difficult cross-functional engineering problems personally while building processes that scale.

What We Offer

Competitive compensation and meaningful equity, ownership of critical silicon programs, and the chance to build a world-class ASIC organization at the frontier of computing.

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