Search jobs

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

SiTime is looking for a Staff Analog Design Engineer to join a talented analog design team developing advanced clock and timing products. You will lead the development of key circuit blocks from specification through proven silicon. This role requires a solid understanding of top-level architecture and system-level requirements. You will collaborate closely with product development teams and support validation, qualification, and new product release.

Responsibilities

• Develop specifications and design analog circuits for high-performance timing products
• Incorporate circuit blocks into the complete chip design
• Collaborate with distributed cross-functional teams, including layout, digital, system design, and validation
• Test, debug, and characterize lab prototypes
• Support product validation and customer applications

Qualifications & Requirements

• Master’s or PhD degree in Electrical Engineering.
• 6+ years of relevant analog/mixed-signal IC design experience.
• Proven experience in CMOS and/or BiCMOS IC design.
• Strong knowledge of integrated circuit design, device physics, and advanced process technologies
• Experience designing PLLs or related blocks such as VCOs, phase detectors, charge pumps, and supporting circuits
• Solid understanding of transistor behavior, circuit noise theory, and phase-noise concepts
• Proficiency with the Cadence analog/mixed-signal simulation toolset
• Familiarity with analog/mixed-signal design flow, simulation methods, design rules and post-layout verification
• Experience with analog behavioral modeling, SystemVerilog, Verilog-A, and AMS