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ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE

This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification.

THE PERSON

The candidate will have an opportunity to work on state of the art verification environment using UVM verification methodology and C. Besides owning block level test bench, the candidate will have opportunity to work on sub system level verification and other aspects of verification such as performance verification, power aware verification.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems .

KEY RESPONSIBILITIES

• Work with senior verification engineers and create test plans for complex IP designs.
• Design testbenches in System Verilog and UVM to complete verification of the design in an efficient manner.
• Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
• Debug tests with design engineers to deliver functionally correct design blocks and close the coverage.
• Coordinate with RTL engineers to implement logic design for better clock gating and verify the various aspects of the design
• Responsible for verification quality metrics like pass rates, code coverage and functional coverage

PREFERRED EXPERIENCE

• Project level experience with design concepts and RTL implementation for same
• Good understanding of computer organization/architecture and digital logic fundamental's
• Knowledge of object oriented concepts and programming languages like System Verilog, C++
• Hands on Python scripting for automation
• Prior experience in protocol, such as PCIE, AMBA AXI, is a plus