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Volantis Semiconductor, Inc.

Physical Design Engineer

  • Seen live on Volantis Semiconductor, Inc.'s site 3 days ago
  • Mid level
  • Remote
Pay
Not stated
Location
Hybrid Remote/SF Bay Area/Austin/Boston
Open for
12+ days
First seen
Oct 23, 2026
Apply on Volantis Semiconductor, Inc.'s site (opens in a new tab)

Posting record

No flags

Open 12+ days

The posting's record, oldest first
  1. Volantis Semiconductor, Inc.'s site dates the posting
  2. Ghostless first sees this listing
  3. Last checked: still up
How we know

It hasn't been reposted, listed twice, or left up unusually long, and the posting doesn't say it's a talent pool.

Ghostless records the day it first sees a posting, so a repost can't reset its age. This one was already up when Ghostless started tracking Volantis Semiconductor, Inc., so its true age is longer.

Last checked Nov 1, 2026.

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What the posting discloses

Not stated: Pay, real vacancy, AI screening.

Why these three

Ontario requires postings from employers with 25 or more staff to state the pay, whether the vacancy exists, and whether AI screens applicants.

Some employers add pay only on their own site. Check the original posting before you rule it out.

Skills mentioned

About the role

What We’re Looking For

We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort.

Ideal Candidates

Ideal candidates will have

  • Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts
  • Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them
  • Experience both with in-house and outsourced physical design flows

Nice to Have

  • Experience with physical design process for multi-die/multi-chiplet/MCM designs
  • Experience with physical design process for reticle-max or near reticle max designs
  • Experience with very high power density chips
  • Experience with the physical design process for AI chips
  • Experience with the physical design process of analog and mixed signal blocks and macros

Something wrong with this posting?