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Elevate Semiconductor

Senior Analog Design Engineer

  • Seen live on Elevate Semiconductor's site 3 days ago
  • Senior
Pay
$125k to $145k a year USD
Location
San Diego, California, United States
Open for
11+ days
First seen
Oct 24, 2026

Posting record

No flags

Open 11+ days

The posting's record, oldest first
  1. Elevate Semiconductor's site dates the posting
  2. Ghostless first sees this listing
  3. Last checked: still up
How we know

It hasn't been reposted, listed twice, or left up unusually long, and the posting doesn't say it's a talent pool.

Ghostless records the day it first sees a posting, so a repost can't reset its age. This one was already up when Ghostless started tracking Elevate Semiconductor, so its true age is longer.

Last checked Nov 1, 2026.

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What it asks of you

5+ years of experience
“5+ years of professional experience in analog IC design” (quoted from the posting)

What the posting discloses

Pay
$125k to $145k a year USD
The anticipated annual base salary range for this position is $125,000.00 to $145,000.00 . (quoted from the posting)

Not stated: Real vacancy, AI screening.

Why these three

Ontario requires postings from employers with 25 or more staff to state the pay, whether the vacancy exists, and whether AI screens applicants.

Skills mentioned

About the role

As a Senior Analog Design Engineer, you will contribute to the design and optimization of analog circuits used in high performance ATE products. You will work closely with cross functional teams and take ownership of circuit blocks from concept through silicon validation.

In this role, you will apply strong analog design fundamentals to solve complex technical challenges, make design tradeoffs, and drive performance, reliability, and manufacturability. You will contribute throughout the full IC development lifecycle while collaborating with experienced engineers across design, layout, test, and product engineering.

Responsibilities

  • Design and simulate high speed, precision CMOS circuits for ATE applications
  • Perform layout, verification, and post layout simulation, including Monte Carlo, SOAC, and corner analysis
  • Perform mixed signal simulations at both the channel and chip levels
  • Develop and optimize circuit architectures for power, performance, and density
  • Support IC characterization, test development, and qualification
  • Collaborate with cross functional teams including digital design, layout, test, product, and applications engineering

Requirements

  • Bachelor’s degree in Electrical Engineering or related field
  • 5+ years of professional experience in analog IC design
  • Strong foundation in analog CMOS circuit design
  • Experience designing and analyzing feedback loops, including stability analysis and compensation
  • Solid understanding of the full IC development lifecycle, from design and verification through qualification and manufacturing
  • Hands on experience with analog and mixed signal EDA tools such as Cadence, Mentor Graphics, or Tanner
  • Experience performing LVS and DRC verification using Cadence or Mentor tools

The anticipated annual base salary range for this position is $125,000.00 to $145,000.00 . Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.

In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.

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