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Elevate Semiconductor

Staff Analog IC Layout Engineer (Block & Chip)

  • Seen live on Elevate Semiconductor's site 3 days ago
  • Senior
Pay
$145k to $175k a year USD
Location
San Diego, California, United States
Open for
11+ days
First seen
Oct 24, 2026
Apply on Elevate Semiconductor's site (opens in a new tab)

Posting record

No flags

Open 11+ days

The posting's record, oldest first
  1. Elevate Semiconductor's site dates the posting
  2. Ghostless first sees this listing
  3. Last checked: still up
How we know

It hasn't been reposted, listed twice, or left up unusually long, and the posting doesn't say it's a talent pool.

Ghostless records the day it first sees a posting, so a repost can't reset its age. This one was already up when Ghostless started tracking Elevate Semiconductor, so its true age is longer.

Last checked Nov 1, 2026.

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What it asks of you

8+ years of experience
“Minimum of 8 years of professional experience in analog and mixed-signal IC layout design” (quoted from the posting)

What the posting discloses

Pay
$145k to $175k a year USD
The anticipated annual base salary range for this position is $145,000.00 to $175,000.00 . (quoted from the posting)

Not stated: Real vacancy, AI screening.

Why these three

Ontario requires postings from employers with 25 or more staff to state the pay, whether the vacancy exists, and whether AI screens applicants.

Skills mentioned

About the role

As a Staff Analog Layout Engineer, you will take technical ownership of the physical layout and verification of complex analog and mixed-signal integrated circuits for the ATE market. You will work across both block-level and full-chip layout using advanced process technologies ranging from 65nm CMOS to 100+V BCD.

This role offers the opportunity to solve complex layout challenges, collaborate closely with analog design engineers, and influence layout strategy across projects. You will apply your expertise in matching, parasitics, reliability, and manufacturability while helping establish best practices and drive designs through successful tapeout.

Responsibilities

  • Perform physical layout of analog and mixed-signal integrated circuits at both the block and full-chip level
  • Develop floorplans and optimize component placement for area, performance, and power
  • Perform LVS and DRC verification to ensure layout accuracy and compliance with process design rules
  • Collaborate closely with design engineers to translate circuit requirements into high-quality physical layouts
  • Partner with digital design, packaging, and other cross-functional teams to optimize overall chip performance
  • Troubleshoot and resolve layout, verification, and manufacturability issues

Requirements

  • Bachelor’s degree in Electrical Engineering or a related field
  • Minimum of 8 years of professional experience in analog and mixed-signal IC layout design
  • Strong understanding of analog CMOS circuits and device physics
  • Solid knowledge of the IC design, qualification, and manufacturing lifecycle
  • Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner
  • Proficiency in LVS and DRC verification using Cadence or Mentor tools

Preferences

  • Experience with high-voltage (100V+) BCD, LDMOS, and STI layout
  • Experience with mixed-voltage designs involving multiple supply rails and power domains
  • Experience with high-speed, multi-Gbps circuit layout
  • Experience with high-accuracy and precision analog circuit layout
  • Experience with high-resolution data converter layout
  • Experience with BiCMOS process technologies
  • Programming and scripting experience, particularly with SKILL and Calibre scripts

The anticipated annual base salary range for this position is $145,000.00 to $175,000.00 . Actual compensation will be determined based on factors such as experience, skills, qualifications, education, location, and business needs.

In addition to base salary, employees may be eligible for incentive compensation and a comprehensive benefits package. This salary range represents the Company's good-faith estimate of the compensation it reasonably expects to pay for this position at the time of posting.

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