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Location: Burlington, Canada

Our Team

Semtech's Product Quality Engineering team is responsible for the quality and reliability of every wafer that leaves our fabs and OSAT partners on its way to customers. Our engineers thrive on solving complex technical challenges and driving improvements that directly impact product reliability and customer satisfaction including building a new generation of statistical and data-driven tools to detect, characterize, and triage wafer-level quality issues faster and more consistently than manual review alone can achieve. You'll join a team where mentorship, technical excellence, and knowledge sharing create a culture of growth, innovation, and tangible impact.

Job Summary

The Senior Quality Process Development Engineer will collaborate on the design, development, and validation the statistical and machine-learning systems at the core of Semtech's quality processes along with our tool software partners. This role will define the technical development specifications for quality process improvement activities; including detection and pattern-recognition capabilities that distinguish genuine product and process issues from test-induced artifacts, and that support downstream risk assessment and mitigation for production wafer lots. The engineer will work closely with our tool development partners, internal AI team, Quality Engineering, Product Engineering, and the in-house wafer assessment tool development team to integrate these capabilities into existing production systems and will build learned pattern-recognition models from engineer-confirmed labels to complement rules-based statistical detection.

Responsibilities

• Design and build statistical and algorithmic detection tools for wafer probe data — including test hardware integrity checks, software bin/yield outlier detection, parametric drift analysis, and reticle- and wafer-level spatial pattern classification — leveraging Semtech's existing statistical infrastructure (20%)
• Assist on the development of learned pattern-recognition models that classify wafer-level failure patterns from engineer-confirmed examples, complementing the statistical tool set and supporting multi-pattern classification with confidence indicators. Risk-tiering, prioritization, and mitigation-proposal logic — including known-issue catalog matching, lot-level systemic risk reporting, and drafting of wafer-map modification scripts (20%)
• Drive along with the tool software teams the buildup of relationship-analysis and reporting layer that reconciles detection outputs into a consolidated set of distinct issues, including LLM-driven contextualization using product and test/bin naming data, and structured, self-describing output for downstream risk assessment (20%)