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ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE

Join an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies. You will work closely with RTL design and other engineering partners throughout the project lifecycle, from floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and final signoff. The role also provides opportunities to lead technical execution, establish design methodologies, improve automated design flows, and mentor other engineers.

THE PERSON

You are a collaborative technical leader who brings strong analytical thinking, clear communication, and attention to detail to complex physical design challenges. You work effectively with RTL and physical design teams to solve problems, navigate technical tradeoffs, and keep designs moving toward closure. You take ownership of execution, communicate issues and priorities clearly across geographically distributed teams, and are comfortable providing technical guidance and mentoring to other engineers. You can balance multiple priorities while keeping the team focused on successful project delivery.

KEY RESPONSIBILITIES

• Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
• Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
• Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
• Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
• Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
• Drive design optimization for timing, power, area, and design-cycle efficiency.